Hardware designs, such as system-on-chip (SoC) designs, are typically verified (i.e. determined to meet their specifications) before they are implemented in silicon because post-silicon error discovery can be very expensive. Hardware designs are often optimized for performance, power and area which can lead to a design which may end up in a lockup or deadlock state. A lockup or deadlock state is one that once reached, no combination of inputs, or combination of internal state interactions will cause the state to be exited (i.e. it is not possible to transition out of the state). A deadlock state occurs due to multiple contenders competing for resource utilization, hazard avoidance, performance boost or fine tuning area. A key requirement in any verification of a hardware design is to ascertain that there is no deadlock in the design.
Ideally deadlock detection in hardware designs comprises exhaustively analyzing all the states in a design, which takes a significant amount of time and resources to complete. However, due to the dominance of simulation based verification, in practice scoreboards and monitors are used to track the global end-to-end behavior of the design. If there is a deadlock in the design that can be triggered by a test bench stimulus then the deadlock may stall one or more transactions and therefore the states related to these transactions will not update as expected in the global scoreboard. For example, within a certain timeout period some transactions may not have been completed. This is discovered only at the end of the simulation when all of the tests have been completed, aborted or failed. Accordingly, the main problem with using simulation based verification to identify deadlock is that deadlock is not identified until the end of the simulation which makes it difficult to identify the source of the deadlock.
The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known verification systems.